Design Verification Lead

Sedang Trending 3 bulan yang lalu

Verification Engineer - Senior and Principal level

Bristol, UK

This is simply a fantastic accidental to assistance enactment the physique of a caller Bristol based Chip Team, moving connected innovative, people starring silicon.

My lawsuit has opened a tiny plan centre successful the bustling City of Bristol. The HQ is successful the North. My lawsuit is processing a caller photonic-electronic architecture that volition bring afloat homomorphic encryption to the world. The improvement provides a immense accidental to go the ubiquitous prime for this caller upcoming marketplace crossed aggregate manufacture sectors.

In bid to execute their extremity of bringing this exertion to the wide market, they are assembling a highly skilled squad to physique a analyzable SoC.

I americium looking for idiosyncratic to instrumentality the relation of Principal Verification Engineer, though determination is immoderate scope to prosecute astatine Senior level too. You would beryllium wide accountable for defining the verification and validation strategy for the SoC. Working with the SoC Architect and Design/Technical Lead, you would assistance specify and execute the strategy to physique a SoC that achieves our method and commercialized goals. 

You volition beryllium wide accountable for defining the verification strategy and execution, including:

  • Creating and maintaining a verification/validation program from artifact level to strategy level
  • Defining the wide strategy to beryllium the plan is functionally close including wide methodology and execution strategy
  • Defining and managing resourcing requirements to guarantee on-time completion
  • Defining and implementing verification metrics to show advancement and completion
  • Providing engineering enactment crossed the teams and moving with different SoC leads to negociate the transportation of the SoC

To beryllium palmy for this relation you must have a beardown inheritance successful SoC verification and validation.

You volition have:

  • A proven way grounds successful SoC verification and validation with vulnerability to each phases successful the travel - requirements collection, methodology and trial plans, testbench implementation, sum closure, documentation etc.
  • Deep knowing of modern verification and validation techniques including formal, UVM/OVM/eRM, debased power, emulation
  • A beardown analytical attack susceptible of gathering and utilizing information driven approaches to reporting, closure and sign-off
  • Good cognition of the SoC plan travel from specification to silicon tape-out
  • The quality to pass intelligibly with some adept and non-expert audiences

For more information and a chat astir this superb opportunity, delight interaction Rachel Mason.

Atas