Digital IC Design Engineer

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Job Overview

To fortify their existing IC plan team, my lawsuit are presently looking for a inferior integer IC designer. The technologist requested for this presumption volition beryllium liable for design, simulation and afloat validation of respective programmable functional units wrong a analyzable IC device, which is astatine the halfway of their flagship powerfulness adapter product. you volition beryllium reporting to the caput of the IC team. The selected idiosyncratic volition enactment successful adjacent collaboration with our R&D squad for the improvement of caller IPs to beryllium integrated into the adjacent procreation ASICs.

Main Responsibilities:

You should beryllium a motivated and proactive engineer, capable to enactment good wrong an autarkic squad and acceptable to beryllium progressive in:

  • VHDL / Verilog / System-Verilog plan astatine RT-Level of halfway functional blocks
  • Implementation of RTL-to-Syn IC plan flow, including timing/power analysis
  • Testbench plan successful system-verilog (UVM compliant)
  • Verification of integer IPs utilizing simulation tools astatine antithetic abstraction level (from RTL to post-layout)
  • Co-simulation of integer and analog IPs to validate the full mixed-signal system
  • FPGA prototyping of halfway integer IPs
  • Silicon validation activities with laboratory instrumentation

Qualifications and Background

  • PhD oregon MS Degree successful Microelectronics oregon Physics
  • 3-10+ years related experience
  • Strong cognition of the CMOS technology, modular logic libraries and manufacturing process
  • Good cognition of VHDL oregon Verilog oregon System-Verilog language
  • Basic cognition of programming and scripting languages similar C++, TCL, bash, Perl
  • Good acquisition of translating plan requirements into RTL description
  • Experience of integer oregon mixed-signal verification activities, testbench and verification planning, regression tests
  • Consolidated cognition connected implicit ASIC plan travel (from RTL to GDSII)
  • Good cognition of existing EDA tools (Cadence oregon Synopsys Design Framework)
  • Good English cognition (written and spoken)

Nice to have

  • Basic cognition of immoderate modelling languages similar Verilog-A oregon VHDL-AMS
  • Good cognition of microprocessor plan (architecture, explanation of a customized ISA, implementation data/memory bus)

Contact Name: Rob Hudson

Reference: TJ/801/V-190097

Job ID: 3313874

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