Digital Verification Engineer - UVM

Sedang Trending 1 bulan yang lalu

Premium Job From IC Resources

Working for an breathtaking fabless semiconductor company, the palmy Digital Verification Engineer volition enactment successful a challenging method situation connected the plan of a state-of-the-art CMOS Transceiver ASIC for the communications market.

The campaigner volition beryllium progressive successful the verification of the integer processing functions of the ASIC successful adjacent collaboration with the mixed-signal and integer IC plan engineers.

Qualification and experience 

  • You person a MSc oregon PhD successful Electrical Engineering oregon equivalent and 3+ years of hands-on acquisition successful integer IC verification
  • You person coagulated cognition of a integer hardware statement languages (VHDL oregon Verilog) and scripting languages (TCL, Perl, Python)
  • You person coagulated cognition of System Verilog and UVM methodology & processes
  • Experience successful ceremonial verification and gate-level simulations are a plus
  • A erstwhile acquisition successful verification of integer functions for Mixed-Signal ICs specified arsenic A/D Converters, D/A Converters, and/or RF transceivers is simply a plus
  • Good cognition of Cadence oregon Synopsys RTL plan tools
  • A erstwhile acquisition with FPGA is simply a plus
  • You are a squad subordinate with a captious cognition and consciousness of initiative
  • You pass fluently successful English (oral and written)

For much information, delight contact  Click present to interaction this recruiter Resources

Contact Name: Lucy Edmondson

Reference: TJ/801/V-192487

Job ID: 3313057


You are presently utilizing an outdated browser.

Please see utilizing a modern browser specified arsenic 1 listed below: