Lead RF IC Design Engineer

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This is an accidental for a Lead RF IC Design oregon MMIC Designer to articulation an expanding institution moving processing precocious tech communications and radar technologies.

In this relation you volition person the accidental to enactment connected antenna exertion to service markets including; broadband mobility, outer communications and Internet of Things (IoT).

As the Lead RF IC Design Engineer you volition beryllium taking a pb relation liable for starring the plan of Ku/Ka set RF Transmitters & Receivers utilizing heavy sub-micron technologies for adjacent procreation of outer communications and volition beryllium liable for transportation of ASIC Specifications, architecture design, circuit plan & verification, review, IC qualification & accumulation release.

You volition beryllium starring and mentoring a squad of RF IC Design engineers and volition enactment intimately crossed the organisation from layout & trial teams to systems, antenna, hardware teams to guarantee on-time transportation of starring ASICs. You volition besides assistance successful choosing the fabrication process & exertion vendors, setup process travel and ensuring plan governance, make merchandise improvement plans and exertion roadmaps.

Industry grade qualified you volition person a minimum of 10 years of acquisition successful the plan of RF ICs successful heavy sub- micron technologies (preferably 15GHz oregon higher operating frequencies) with spot pb acquisition successful 2 oregon much palmy tape-outs.

Responsibilities Include:

  • ASIC specifications, architecture design, apical level plan & verification, artifact level designs and on-time tape-out of ASICs.
  • Design of transmitter & receiver blocks successful Ku/Ka set successful heavy sub- micron CMOS technologies.
  • Hands-on block-level plan of assorted RF blocks specified arsenic PA, LNA, VGA, Phase shifters, Power Splitters/combiners.
  • Delivering precocious prime RF/Analog blocks with starring borderline show utilizing innovative architectures and circuit implementations.
  • Co-ordinate and negociate plan activities with different colleagues.
  • Collaborate with CAD, process technology, bundle design, Antenna & hardware teams.
  • Document ain enactment and pb plan reviews.
  • Experience is desired successful 22nm FDSOI oregon different sub 45nm CMOS process nodes for RF/High velocity ICs and/or acquisition successful mmW/RF IC design, LNA plan and RF PAs.

Excellent connection skills are required arsenic good arsenic the quality to instrumentality work for analyzable circuit and strategy designs wrong transportation timescales. You volition person the quality to interact with engineering teams crossed aggregate disciplines during ASIC task watercourse development.

Visa sponsorship is disposable for the palmy applicant.

Contact Leon to use and find retired more.

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