Senior Digital Design Engineer (ASIC / NOC / SOC)

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Exciting accidental arsenic Senior Digital IC Design Engineer to articulation the satellite person successful network-on-chip interconnect exertion integration and deployment for SoCs. 

Located successful offices to the westbound of Paris, my lawsuit provides semiconductor intelligence spot (IP) for immoderate of the champion known brands successful the satellite - covering a wide scope of applications from AI to cars, mobile phones, IoT, cameras, and SSD controllers. 

As Senior Digital IC Design Engineer, your cardinal task volition beryllium to make IPs for lawsuit specifications, moving intimately with the verification squad to resoluteness immoderate issues. 

Key responsibilities:

  • Write micro-architecture specification for highly configurable IPs
  • Develop oregon upgrade IPs RTL statement with performance, power, country goals
  • Communicate with Software, Modeling and Documentation teams astir your changes to guarantee merchandise cohesion
  • Help amended and refine processes, methodologies, and metrics

Experience requirements / qualifications:

  • 5+ years of manufacture acquisition arsenic an RTL Design Engineer - ASIC / SOC / FPGA
  • Knowledge of Verilog oregon SystemVerilog.
  • Knowledge of interconnect exertion is simply a plus
  • Knowledge of Cache architecture is simply a plus.
  • Knowledge of AMBA protocols, ARM/MIPS processors, on-chip interfaces specified arsenic OCP & AXI
  • Experience with C / C++ oregon Python oregon JavaScript is simply a plus.
  • Good written and verbal connection skills successful some French and English
  • Positive cognition and attack to the work

Education requirements:

  • Engineering Master's Degree

To larn more, oregon apply, delight contact Lucy Edmondson @ IC Resources.

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