Senior UVM Verification Engineer

Sedang Trending 1 bulan yang lalu

Are you looking for the adjacent measurement successful your vocation successful UVM Verification? Would you similar to larn from skilled experts successful a affable and increasing situation with breathtaking projects? If the reply is yes, past this whitethorn beryllium the cleanable accidental for you!

I person a cardinal request for an experienced Senior UVM Verification Engineer to enactment for an established institution based successful the Grenoble country who absorption connected plan and verification services for a fig of large clients.

As the Senior UVM Verification Engineer, you volition beryllium liable for R&D projects and the improvement of verification environments (SystemVerilog / UVM /…), VIP components and giving grooming to different engineers.

Technical skills

  • 3-5+ years' IP oregon SoC verification experience
  • Confident cognition with SystemVerilog and UVM methodology
  • SoC architecture  
  • Bus connection protocols cognition - AMBA / AXI etc.
  • OOP (Object Oriented Programming) and scripting skills / hardware & bundle - perl / shel / python / c
  • Fluent English and preferably French
  • Master's Degree - this is simply a bonus

If you would similar to cognize more, delight contact Lucy Click present to interaction this recruiter Resources for a discussion.

Atas